Method and apparatus for designing and integrated circuit

ABSTRACT

Method and apparatus for designing an integrated circuit by adding a plurality of control points to an integrated circuit wafer design. Each control point has at least one attribute. Then, an integrated circuit wafer is manufactured using the integrated circuit wafer design. A defect on the integrated circuit wafer is then located. The control points are adjusted such that they correspond with the defect.

FIELD OF THE INVENTION

The present invention relates to a method and apparatus for designing anintegrated circuit.

BACKGROUND OF THE INVENTION

When making an integrated circuit (which may also be referred to as anIC, chip or device), a design layout of the IC is made using, forexample, CAD tools. A reticle or mask is then produced for the IC designlayout and then photolithography is used to transfer features from thereticle or mask to a die (integrated circuit semiconductor wafer).

Various techniques are used to reduce the level of defects in theresultant die. For instance, prior to the production of the reticle, thedesign layout may be optimized using optical proximity correction (OPC)to create a reticle layout. This optimization process amends thephysical design layout in order to avoid optical or process distortionsalso known as patterning defects when features are transferred from thereticle or mask that may cause failures of the device. The OPCoptimization process discretizes the design layout into moveablesegments and adds control points to the design where it is determinedthat patterning defects may occur. The segmented features of the ICdesign are then amended using a model of the patterning process tocalculate patterning error information at these control points until itis determined that the patterning defects are fixed. Once the patterningdefects are fixed there is no further use for the control points.

Once the reticle is produced and wafer dies have been manufactured,features on these wafer dies may be measured or micrographed by scanningelectron microscope (SEM) techniques to evaluate if there are patterningdefects which were not adequately fixed during OPC. Obviously,individually measuring or micrographing each feature on a multi-milliongate device is unfeasible. Therefore, certain representative featuresare chosen. These representative features can be determined byrule-based guidelines or by lithographic simulation predictions.

Where wafer patterning defects are found that would result in anunacceptable failure rate for the IC, the reticle layout must beadjusted to avoid these critical defects. This results in furtheriterations of OPC, build and test of the die until no critical defectsare found or the die meets other success criteria. This is a costly andlabor intensive process and may result in many time consuming iterationsuntil a successful reticle layout is found.

SUMMARY OF THE INVENTION

The present invention provides a method and apparatus for designing anintegrated circuit as described in the accompanying claims.

BRIEF DESCRIPTION OF THE FIGURES

The present invention may be put into practice in a number of ways andan embodiment will now be described by way of example only and withreference to the accompanying drawings, in which:

FIG. 1 shows a schematic diagram of a layout of a portion of anintegrated circuit according to an embodiment of the present invention,including control points at particular locations, given by way ofexample;

FIG. 2 shows a SEM image of a portion of the integrated circuitcorresponding to the portion shown in FIG. 1, given by way of example;

FIG. 3 shows a schematic diagram of the layout of the portion of theintegrated circuit shown in FIG. 1 but with control points in differentlocations, given by way of example;

FIG. 4 shows a SEM image of a portion of the integrated circuitcorresponding to the portion shown in FIG. 3, given by way of example;and

FIG. 5 shows a flowchart of a method for designing an integrated circuitaccording to an embodiment of the present invention, given by way ofexample.

It should be noted that the figures are illustrated for simplicity andare not necessarily drawn to scale.

DETAILED DESCRIPTION OF AN EMBODIMENT

FIG. 1 shows a schematic diagram of the layout 10 of several featuresforming part of an integrated circuit (IC). The IC layout is designedusing known CAD tools and may be optimized using an optical proximitycorrection (OPC) technique. OPC may be used to reduce the adverseeffects of optical and process distortions occurring during fabricationof a wafer.

During the OPC process certain feature locations may be identified aspotential areas for causing defects in the wafer leading to failure ofthe IC. For instance, the areas around bends in a track may be producedtoo thin to the extent that they cannot conduct a high enough electricalcurrent leading to burn-out at this point. These potentially problematicfeature locations may be tagged by the addition of control points to thedesign. These control points are used to reference particular featurelocations and are not fabricated on the final wafer. The control pointsare used during the OPC optimization process to amend particularfeatures.

In the method in accordance with the present invention, the controlpoints are also used during wafer patterning defect evaluation. The useof control points during wafer patterning defect evaluation is not knownfrom previous techniques. In one embodiment, instead of discarding thecontrol points after the OPC optimization process is completed, thecontrol points are instead stored for use during wafer patterning defectevaluation. In another embodiment, an algorithm for determiningplacement of the control points may be stored for use during waferpatterning defect evaluation. In yet another embodiment, the controlpoints may be regenerated on a subset of the original layout for useduring wafer patterning defect evaluation.

Control points are locations for calculation of edge position (EP), edgeposition error (EPE), or critical dimension (CD) for wafer features. TheCD of a feature indicates the width at a specific location on thatparticular feature or the space at a specific location between twofeatures. The EP, EPE or CD for any particular location may be estimatedduring the OPC optimization step. During a step in the OPC optimizationprocess the EPs, EPEs or CDs for potentially problematic features arecalculated at the control points. Therefore, each control point willhave certain attributes that may be recorded for later retrieval. Theseattributes include location, tolerance, critical dimension, EP, EPE, CD,size and accuracy. The attributes for the control points may be storedin a database or other suitable computer file format.

Control points are generated during the OPC procedure before themovement of the design segments by the OPC software. Control points aregenerated by an algorithm for determining where OPC segment movementswill be required in a design. To place control points, the algorithm mayuse geometrical rules such as distance from a design corner, or theresults of patterning simulations such as light intensity minima orboth.

FIG. 1 and FIG. 2 illustrate an example situation, where control pointsare not located correctly. This may be due, for example, to deficienciesin the algorithm used to generate control points. For example, ifgeometric rules are used to determine the placement of control pointsnear design corners, the results of the geometric rules may not providefor optimum control point placement when there are many design cornersin close proximity to each other on a given feature. In this example OPCoptimization has not effectively optimized the design layout due to themisplaced control points.

FIG. 1 contains a simulation of a particular problematic feature 20 thathas a pinch point indicated by arrow 30. Three pairs of control points40 surround the pinch point but none line up precisely with it. Thesecontrol points 40 were added during an OPC optimization process.

Once a wafer has been fabricated wafer patterning defect evaluation maybe used to analyze potentially problematic features. These checks mayinvolve measuring the actual minimum wafer CD of problematic featuresand comparing this measurement to a predetermined CD tolerancethreshold. If the actual CD measured is less than the CD tolerancethreshold, a patterning defect may be highlighted. These checks may alsoinvolve measuring the distance between the detected patterning defectlocation and the nearest control point. If this measured distance isgreater than a predetermined threshold distance, a control pointplacement error may be highlighted.

FIG. 2 shows a SEM micrograph of a portion 110 of the IC wafercorresponding to the portion of IC design shown in FIG. 1. CorrespondingSEM feature 20 is shown with control points 40 highlighted. SEM CDmeasurements taken at control points 40 in FIG. 2 may be compared to thepatterning model's prediction of feature 20 CDs at the control points inFIG. 1. The predicted vs. measured CD comparison shows that thepatterning model has sufficient accuracy, as can be seen by comparingthe model predicted feature 20 in FIG. 1 to the SEM image of feature 20in FIG. 2. Dotted lines 50 indicate the measured CD of the pinch pointon feature 20. However, none of the control points 40 are placed at thenarrowest point in feature 20. Thus, although the patterning model hadsufficient accuracy, the OPC optimization failed to identify the mostcritical portion of feature 20 (i.e. the pinch point 30). Furthermore,none of the CDs of the feature 20 measured at each of the control points40 are below the predetermined CD tolerance threshold. This portion ofthe wafer will therefore, pass this particular validation test whenlooking at control points 40 without the most critical feature beingmeasured. Nevertheless, the IC manufactured according to the design mayfail at this point. Further measurements may be made using the SEM andthese measurements will not necessarily use control points 40 butinstead are used to look for features that may potentially causefailures.

FIG. 3 and FIG. 4 illustrate an example situation, where control pointsare placed correctly, i.e. the minimum distance between the controlpoints 40 and the patterning defect location 30 is less than apredetermined threshold value. In this example although OPC optimizationoccurred at the correct location the layout of the feature was notcompensated to a sufficient degree to avoid failures. The failure inthis example to compensate the feature adequately is due to a limitationof the patterning model accuracy. Because of this model inaccuracy,simulated CD, EP or EPE measurements made at the control points may noteffectively test the suitability of the IC design. Again, the controlpoints 40 were positioned during an OPC optimization process.

FIG. 3 shows a similar schematic diagram to that of FIG. 1. However, theportion of the IC design 210 contains only a single pair of controlpoints 240. The control points are located at the correct position, i.e.at the narrowest point of the feature 20. However, the measured CD atthe control points 240 is less than an acceptable CD.

FIG. 4 shows a SEM micrograph of a portion 310 of the IC wafercorresponding to the portion of IC design 210 shown in FIG. 3. Again,the pair of control points 240 are overlaid on this micrograph portion310. The patterning model predicted CD of the feature 20 at controlpoints 240 is greater than the minimum acceptable CD, and so thevalidation test using the control points will pass but as the actualminimum wafer CD of feature 20 measured by the SEM at the control points240 is narrower than the minimum acceptable CD the feature 20 may stillcause a failure once the IC is in use.

Since the attributes of the control points and the accuracy of thepatterning model both affect the success of OPC optimization it maytherefore, be necessary to optimize these attributes and/or the modelaccuracy before subsequent OPC optimization processes commence.

FIG. 5 shows a flowchart showing the steps for designing an IC. FIG. 5is an embodiment of the method according to the invention. Flowchart 400starts after an initial IC design has been completed. Implementation offlowchart 400 reduces the risk of encountering similar situations tothose described with respect to FIGS. 1 to 4.

OPC optimization is run on the initial IC layout design 410. During OPCoptimization control points may be added at a suitable step, to identifypotentially problematic features 420. Control points may be added by analgorithm for determining where OPC segment movements will be requiredin a design. To place control points, the algorithm may use geometricalrules or alternatively, the results of patterning simulations or both.In one embodiment, the control points and their associated attributesmay be stored for later retrieval. In another embodiment, the placementalgorithm may be stored for later regeneration of the control points andtheir associated attributes.

Once an OPC optimization process has been run, an IC wafer may befabricated using the optimized IC design 430.

Then, the IC wafer may be examined using a SEM or other suitable imagingor scanning technique in order to locate defects 440. The potentialdefect locations to examine with the SEM may be determined usingsimulation analysis of the OPC optimized design, using a wafer baseddefect detection method such as die-die optical wafer inspection, by areview of programmed potential defective structures such as structuresdrawn at design rule limits, or other suitable detection method. If nodefects are found the process may stop and the wafer may go into fullproduction in the usual way.

The portion of the IC layout design containing a defect found in step440 may be added to a tuning feature set 480 and used to find similardefects during subsequent optimization of previous IC designs, of thisIC design or of future IC designs. For example, a portion of a layoutcontaining a defect found in step 440 may be compared against otherdesigns using pattern matching algorithms in order to determine if thesedesigns will contain the same defect. In another example, the portion ofthe layout containing a defect found in step 440 can be placed into afeature set used for training empirical process models. In yet anotherexample, the portion of the layout containing a defect found in step 440can be placed into a feature set for optimizing or verifying OPCcharacteristics such as control point placement. If defects are found itmay be determined whether or not they correspond to control points orpairs of control points 450. If the defects do not correspond toexisting control points this indicates that the OPC process may havemisplaced the control points. For instance, the control points may be inthe wrong locations (see FIGS. 1 and 2 and the correspondingdescription). In this case control points may be moved or added to thedefective feature 460 to ensure that control points correspond to thedefective feature. In a further embodiment of the method of theinvention step 480 may be left out.

The algorithm for placing control sites may be rebuilt 490 using thelayout portion containing a defect found in step 440. In a furtherembodiment of the method of the invention step 490 may be left out.

After it is known that control points correspond to the defectivefeature, simulated measurements of CD, EP or EPE can be taken at thedefect location using the process model. The simulated results can becompared to the SEM measurements at the defective location 470. If thedifference between the SEM measured and process model predicted results470 is less than a predetermined threshold value, the process may stop.If the difference between the SEM measured and process model predictedresults 470 is greater than a predetermined threshold value, then thisindicates the process model has insufficient accuracy and should beamended or rebuilt 500. The process model may be rebuilt using thefeature set used for training empirical process models. The processmodel uses an empirical model or function which is used to transform oranalyze an approximate physically based simulation of light intensityand to predict CD, EP, EPE or other OPC parameters. Some process modelparameters may be empirically fit to match experimental SEM CD, EP orEPE data using a set of model training layout structures. Possiblereasons for discrepancies in measured vs. process model predicted valuesinclude insufficient training layout structure coverage, poor empiricalparameter values, and poor physical approximations in simulated lightintensities.

If the process model is amended or rebuilt, the stored attributesassociated with the incorrect control points will require updating. Oncethe process model is improved, the OPC process may be re-run and theprocess repeated until all significant defects have been removed. It maybe possible to carry out a partial OPC optimization rather than tooptimize the entire IC design. For repeated structures, updates to oneinstance may be duplicated for all instances.

In this way the information used to generated control points during OPCoptimization may be re-used and tuned to further optimize the OPCprocess. This results in a more efficient design process and a finaldesign may be found using fewer OPC, build and test cycles.

The method described above may be carried out in an automated mannerusing suitable apparatus or a computer programmed to perform each of themethod steps.

As will be appreciated by the skilled person, details of the aboveembodiment may be varied without departing from the scope of the presentinvention, as defined by the appended claims.

For example, the control points may be added to the design at anotherstage in the design process rather than during OPC optimization.

The defects that may be detected include tracks that are too narrow toallow sufficient current to flow, tracks that are too close together,tracks that are too short or weak connections.

Defects may be found on the wafer using various techniques includingscanning electron microscope measurements.

The separation of a pair of control points may be used to define anestimated CD for a particular feature.

Control points may be used to assist with the location of defects on thewafer as they may be located in proximity to parts of featuressusceptible to defects.

1. A method of designing an integrated circuit comprising the steps of:adding a plurality of control points to an integrated circuit waferdesign, wherein each control point has at least one attribute;manufacturing an integrated circuit wafer using the integrated circuitwafer design; locating a defect on the integrated circuit wafer;adjusting the plurality of control points such that they correspond withthe defect.
 2. The method of claim 1, wherein the adjusting step furthercomprises changing the at least one attribute.
 3. The method of claim 2,wherein the adjusting step further comprises adding a control point. 4.The method of claim 2, further comprising the step of recording aportion of the integrated circuit design containing the defect, in atuning feature set.
 5. The method of claim 2, wherein the plurality ofcontrol points are added during an optical proximity correction (OPC)optimisation process.
 6. The method of claim 1, wherein the at least oneattribute is selected from the group consisting of location, tolerance,critical dimension (CD) edge position (EP) edge position error (EPE) andsize.
 7. The method of claim 6, wherein the at least one attribute isselected from the group consisting of location, tolerance, criticaldimension (CD) edge position (EP) edge position error (EPE) and size. 8.The method of claim 6, wherein the plurality of control points are addedduring an optical proximity correction (OPC) optimisation process. 9.The method of claim 1, wherein the adjusting step further comprisesadding a control point.
 10. The method of claim 1, further comprisingthe step of recording a portion of the integrated circuit designcontaining the defect, in a tuning feature set.
 11. The method of claim1, wherein the plurality of control points are added during an opticalproximity correction (OPC) optimisation process.
 12. The method of claim1, further comprising the step of storing the plurality of controlpoints.
 13. The method of claim 1, further comprising the step ofdetermining an error between a process model prediction of the at leastone attribute and a physical measurement of the at least one attribute.14. The method of claim 13, wherein the determining the error stepfurther comprises comparing the error within a predetermined thresholderror value to determine if the process model should be amended.
 15. Themethod of claim 13, wherein the physical measurement is a scanningelectron microscope (SEM) measurement.
 16. The method of claim 1,wherein the locating step is performed using a scanning electronmicroscope (SEM).
 17. A computer program comprising program instructionsthat, when executed on a computer cause the computer to perform themethod of claim
 1. 18. An integrated circuit manufactured according tothe method of claim
 1. 19. Apparatus for designing an integrated circuitcomprising: a computer system to add a plurality of control points to anintegrated circuit wafer design, wherein each control point has at leastone attribute; a defect tool to locate a defect on the integratedcircuit wafer manufactured using the integrated circuit wafer design;the computer system to adjust the plurality of control points such thatthey correspond with the defect.
 20. The apparatus of claim 19, whereinthe defect tool comprises an error is a scanning electron microscope(SEM).